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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8591/ad8592/ad8594 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 cmos single supply rail-to-rail input /output operational amplifiers with shutdown pin configurations 6-lead sot (rt suffix) 6 4 1 2 3 out a 2 in a v 1 v 2 1 in a 5 sd ad8591 10-lead m soic (rm suffix) sda sdb 5 6 vC +in b 4 7 out a Cin a +in a v+ out b 1 2 3 10 9 8 Cin b ad8592 (not to scale) 16-lead narrow soic (r suffix) top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 nc = no connect out a 2 in a v 1 1 in a 1 in b 2 in b out b nc out d 2 in d 1 in d v 2 1 in c 2 in c out c sd ad8594 16-lead tssop (ru suffix) nc sd out a 2 in a 1 in a v 1 2 in d 1 in d v 2 out d 1 1 in b 2 in b out b 2 in c out c +in c 16 ad8594 1 89 nc = no connect features single supply operation: +2.5 v to +6 v high output current: 6 250 ma extremely low shutdown supply current: 100 na low supply current: 750 m a/amp wide bandwidth: 3 mhz slew rate: 5 v/ m s no phase reversal very low input bias current high impedance outputs when in shutdown mode unity gain stable applications mobile communication handset audio pc audio pcmcia/modem line driving battery powered instrumentation data acquisition asic input or output amplifier lcd display reference level driver general description the ad8591, ad8592 and ad8594 are single, dual and quad rail - to-rail input and output single supply amplifiers featuring 250 ma output drive current and a power saving shutdown mode. the ad8592 includes an independent shutdown func- tion for each amplifier. when both amplifiers are in shutdown mode the total supply current is reduced to less than 1 m a . the ad8591 and ad8594 include a single master shutdown func- tion that reduces total supply current to less than 1 m a. all amplifier outputs are in a high impedance state when in shut- down mode. these amplifiers have very low input bias currents, making them suitable for integrators and diode amplification. outputs are stable with virtually any capacitive load. supply current is less than 750 m a per amplifier in active mode. applications for these amplifiers include audio amplification for portable computers, portable phone headsets, sound ports, sound cards and set-top boxes. the ad859x family is capable of driving heavy capacitive loads such as lcd panel reference levels. the ability to swing rail-to-rail at both the input and output enables designers to buffer cmos dacs, asics and other wide output swing devices in single supply systems. the ad8591, ad8592 and ad8594 are specified over the indus- trial (C40 c to +85 c) temperature range. the ad8591, single, is available in the tiny 6-lead sot package. the ad8592, dual, is available in the 10-lead m soic surface mount package. the ad8594, quad, is available in 16-lead narrow soic and 16-lead tssop packages.
C2C rev. a ad8591/ad8592/ad8594Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 25 mv C40 c < t a < +85 c30mv input bias current i b 550 pa C40 c < t a < +85 c60pa input offset current i os 125 pa C40 c < t a < +85 c30pa input voltage range 0 +2.7 v common-mode rejection ratio cmrr v cm = 0 v to +2.7 v 38 45 db large signal voltage gain a vo r l = 2 k w , v o = +0.3 v to +2.4 v 25 v/mv offset voltage drift d v os / d t20 m v/ c bias current drift d i b / d t 50 fa/ c offset current drift d i os / d t 20 fa/ c output characteristics output voltage high v oh i l = 10 ma +2.55 +2.61 v C40 c to +85 c +2.5 v output voltage low v ol i l = 10 ma 60 100 mv C40 c to +85 c 125 mv output current i out 250 ma open-loop impedance z out f = 1 mhz, a v = 1 60 w power supply power supply rejection ratio psrr v s = +2.5 v to +6 v 45 55 db supply current/amplifier i sy v o = 0 v 1 ma C40 c < t a < +85 c 1.25 ma supply current shutdown mode i sd all amplifiers shut down 0.1 1 m a C40 c < t a < +85 c1 m a i sd1 amplifier 1 shut down (ad8592) 1.4 ma i sd2 amplifier 2 shut down (ad8592) 1.4 ma shutdown inputs logic high voltage v inh C40 c < t a < +85 c +1.6 v logic low voltage v inl C40 c < t a < +85 c +0.5 v logic input current i in C40 c < t a < +85 c1 m a dynamic performance slew rate sr r l = 2 k w 3.5 v/ m s settling time t s to 0.01% 1.4 m s gain bandwidth product gbp 2.2 mhz phase margin f o 67 degrees channel separation cs f = 1 khz, r l = 2 k w 65 db noise performance voltage noise density e n f = 1 khz 45 nv/ ? hz f = 10 khz 30 nv/ ? hz current noise density i n f = 1 khz 0.05 pa/ ? hz specifications subject to change without notice. (v s = +2.7 v, v cm = +1.35 v, t a = +25 8 c unless otherwise noted)
C3C rev. a ad8591/ad8592/ad8594 electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 225 mv C40 c < t a < +85 c30mv input bias current i b 550 pa C40 c < t a < +85 c60pa input offset current i os 125 pa C40 c < t a < +85 c30pa input voltage range 0+5v common-mode rejection ratio cmrr v cm = 0 v to +5 v 38 47 db large signal voltage gain a vo r l = 2 k w , v o = +0.5 v to +4.5 v 15 30 v/mv offset voltage drift d v os / d t C40 c < t a < +85 c20 m v/ c bias current drift d i b / d t 50 fa/ c offset current drift d i os / d t 20 fa/ c output characteristics output voltage high v oh i l = 10 ma +4.9 +4.94 v C40 c to +85 c +4.85 v output voltage low v ol i l = 10 ma 50 100 mv C40 c to +85 c 125 mv output current i out 250 ma open-loop impedance z out f = 1 mhz, a v = 1 40 w power supply power supply rejection ratio psrr v s = +2.5 v to +6 v 45 55 db supply current/amplifier i sy v o = 0 v 1.25 ma C40 c < t a < +85 c 1.75 ma supply current-shutdown mode i sd all amplifiers shut down 0.1 1 m a C40 c < t a < +85 c1 m a i sd1 amplifier 1 shut down (ad8592) 1.6 ma i sd2 amplifier 2 shut down (ad8592) 1.6 ma shutdown inputs logic high voltage v inh C40 c < t a < +85 c +2.4 v logic low voltage v inl C40 c < t a < +85 c +0.8 v logic input current i in C40 c < t a < +85 c1 m a dynamic performance slew rate sr r l = 2 k w 5v/ m s full-power bandwidth bw p 1% distortion 325 khz settling time t s to 0.01% 1.6 m s gain bandwidth product gbp 3 mhz phase margin f o 70 degrees channel separation cs f = 1 khz, r l = 10 k w 65 db noise performance voltage noise density e n f = 1 khz 45 nv/ ? hz f = 10 khz 30 nv/ ? hz current noise density i n f = 1 khz 0.05 pa/ ? hz specifications subject to change without notice. (v s = +5.0 v, v cm = +2.5 v, t a = +25 8 c unless otherwise noted)
ad8591/ad8592/ad8594 C4C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8591/ad8592/ad8594 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 v output short circuit duration to gnd 2 . . . . . . . . . . . . observe derating curves storage temperature range r, rt, rm, ru packages . . . . . . . . . . . . C65 c to +150 c operating temperature range ad8591/ad8592/ad8594 . . . . . . . . . . . . C40 c to +85 c junction temperature range r, rt, rm, ru packages . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 for supplies less than 5 v the differential input voltage is limited to the supplies. package type u ja 1 u jc units 6-lead sot-23 (rt) 230 92 c/w 10-lead m soic (rm) 200 44 c/w 16-lead soic (r) 120 36 c/w 16-lead tssop (ru) 180 35 c/w note 1 q ja is specified for worst case conditions, i.e., q ja is specified for device in socket for surface mount packages. ordering guide temperature package package model range description option ad8591art C40 c to +85 c 6-lead sot-23 rt-6 ad8592arm C40 c to +85 c 10-lead m soic rm-10 ad8594ar C40 c to +85 c 16-lead soic r-16a ad8594aru C40 c to +85 c 16-lead tssop ru-16 warning! esd sensitive device load current C ma 10 0.1 1k 0.01 d output voltage C mv 0.1 1 10 1 100 1k source sink v s = +2.7v t a = +25 8 c 100 figure 1. output voltage to supply rail vs. load current load current C ma 10 0.1 1k 0.01 d output voltage C mv 0.1 1 10 1 100 10k source sink v s = +5v t a = +25 8 c 100 1k figure 2. output voltage to supply rail vs. load current temperature C 8 c 2 40 2 20 100 0 20406080 supply current/amplifier C ma 0.90 0.50 0.85 0.70 0.65 0.60 0.55 0.80 0.75 v s = +5v v s = +2.7v figure 3. supply current per amplifier vs. temperature typical performance characteristics
C5C rev. a ad8591/ad8592/ad8594 supply voltage C 6 volts supply current/amplifier C ma 0.8 0.7 0 0.75 1.25 3 1.75 2.25 2.75 0.4 0.3 0.2 0.1 0.6 0.5 t a = +25 8 c figure 4. supply current per amplifier vs. supply voltage temperature C 8 c input offset voltage C mv 2 2 2 8 2 50 2 35 85 5254565 2 3 2 4 2 5 2 6 2 7 v s = +5v v cm = +2.5v 2 15 figure 5. input offset voltage vs. temperature temperature C 8 c input bias current C pa 8 2 2 50 2 35 85 5254565 7 6 5 4 3 v s = +2.7v, +5v v cm = v s /2 2 15 figure 6. input bias current vs. temperature temperature C 8 c input offset current C pa 4 2 2 2 50 2 35 85 5254565 3 2 1 0 2 1 v s = +2.7v, +5v v cm = v s /2 2 15 figure 7. input offset current vs. temperature common-mode voltage C volts input bias current C pa 8 7 1 01 5 23 4 5 4 3 2 6 v s = +5v t a = +25 8 c figure 8. input bias current vs. common-mode voltage frequency C hz gain C db 80 60 1k 10k 100m 100k 1m 10m 40 0 20 45 90 135 180 phase shift C degrees v s = +2.7v r l = no load t a = +25 8 c figure 9. open-loop gain and phase vs. frequency frequency C hz gain C db 80 60 1k 10k 100m 100k 1m 10m 40 0 20 45 90 135 180 phase shift C de g rees v s = +5v r l = no load t a = +25 8 c figure 10. open-loop gain and phase vs. frequency frequency C hz output swing C v p-p 5 4 0 1k 10k 10m 100k 1m 3 2 1 v s = +2.7v r l = 2k v t a = +25 8 c v in = 2.5v p-p figure 11. closed-loop output voltage swing vs. frequency frequency C hz output swing C v p-p 5 4 0 1k 10k 10m 100k 1m 3 2 1 v s = +5v r l = 2k v t a = +25 8 c v in = 4.9v p-p figure 12. closed-loop output voltage swing vs. frequency
ad8591/ad8592/ad8594 C6C rev. a frequency C hz impedance C v 80 60 1k 10k 100m 100k 1m 10m 40 0 20 v s = +5v t a = +25 8 c 100 120 140 160 180 200 a v = 10 a v = 1 figure 13. closed-loop output impedance vs. frequency frequency C hz cmrr C db 110 90 50 1k 10k 10m 100k 1m 80 70 60 v s = +5v t a = +25 8 c 100 figure 14. common-mode rejection ratio vs. frequency frequency C hz psrr C db 80 60 1k 10k 100k 1m 10m 40 0 20 v s = +2.5v t a = +25 8 c 100 100 120 140 2 20 2 40 2 60 +psrr 2 psrr figure 15. power supply rejection ratio vs. frequency frequency C hz psrr C db 80 60 1k 10k 100k 1m 10m 40 0 20 v s = +5v t a = +25 8 c 100 100 120 140 2 20 2 40 2 60 +psrr 2 psrr figure 16. power supply rejection ratio vs. frequency capacitance C pf small signal overshoot C % 60 50 0 10 100 10k 1k 30 20 10 40 v s = +2.5v r l = 2k v t a = +25 8 c +os 2 os figure 17. small signal overshoot vs. load capacitance capacitance C pf small signal overshoot C % 60 50 0 10 100 10k 1k 30 20 10 40 v s = +5v r l = 2k v t a = +25 8 c +os 2 os figure 18. small signal overshoot vs. load capacitance 500 ns/div 20mv/div v s = 6 1.35v v in = 6 50mv a v = 1 r l = 2k v c l = 300pf t a = +25 8 c 0v figure 19. small signal transient response 500 ns/div 20mv/div v s = 6 2.5v v in = 6 50mv a v = 1 r l = 2k v c l = 300pf t a = +25 8 c 0v figure 20. small signal transient response 10 0% 500ns 500mv 100 90 v s = 6 1.35v a v = 1 r l = 2k v t a = +25 8 c figure 21. large signal transient response
ad8591/ad8592/ad8594 C7C rev. a 10 0% 500ns 500mv 100 90 v s = 6 2.5v a v = 1 r l = 2k v t a = +25 8 c figure 22. large signal transient response 10 0% 10 m s 1v 100 90 1v v s = 6 2.5v a v = 1 t a = +25 8 c figure 23. no phase reversal frequency C hz current noise density C pa/ hz 1 0.1 0.01 10 100 100k 1k 10k v s = +5v t a = +25 8 c figure 24. current noise density vs. frequency 100 90 10 0% v s = +5v a v = 1000 t a = +25 8 c frequency = 1khz 100 m v/div marker 41 m v/ hz figure 25. voltage noise density vs. frequency 100 90 10 0% v s = +5v a v = 1000 t a = +25 8 c frequency = 10khz marker 25.9 m v/ hz 200 m v/div figure 26. voltage noise density vs. frequency input offset voltage C mv quantity C amplifiers 300 500 400 200 100 C12 C10 C8 C6 C4 C2 0 2 4 v s = +2.7v v cm = +1.35v t a = +25 8 c figure 27. input offset voltage distribution input offset voltage C mv quantity C amplifiers 300 C12 C10 C8 C6 C4 C2 0 2 4 500 400 200 100 v s = +5v v cm = +2.5v t a = +25 8 c figure 28. input offset voltage distribution
ad8591/ad8592/ad8594 C8C rev. a ad8591/ad8592/ad8594 application section theory of operation the ad859x family of amplifiers are all cmos, high output drive, rail-to-rail input and output single supply amplifiers designed for low cost and high output current drive. the parts include a power saving shutdown function making the ad8591/ad8592/ad8594 op amps ideal for portable multimedia and telecom applications. figure 29 shows the simplified schematic for an ad8591/ad8592/ ad8594 amplifier. two input differential pairs, consisting of an n-channel pair (m1-m2) and a p-channel pair (m3-m4), provide a rail-to-rail input common-mode range. the outputs of the input differential pairs are combined in a compound folded-cascode stage, which drives the input to a second differential pair gain stage. the outputs of the second gain stage provide the gate volt- age drive to the rail-to-rail output stage. the rail-to-rail output stage consists of m15 and m16, which are configured in a complementary common-source configuration. as with any rail-to-rail output amplifier, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. also, the maximum output voltage swing is directly proportional to the load current. the difference be- tween the maximum output voltage to the supply rails, known as the dropout voltage, is determined by the ad8591/ad8592/ ad8594 output transistors on-channel resistance. the output dropout voltage is given in figure 1 and figure 2. 50 m a 100 m a 100 m a 20 m a v b2 m5 m8 m12 m15 m16 m11 out m3 m4 m1 inC in+ v b3 m6 m7 m10 20 m a m13 50 m a v+ vC m9 m14 m2 * * ** m337 sd inv * * m340 *note: all current sources go to 0 m a in shutdown mode inv m31 m30 figure 29. ad8591/ad8592/ad8594 simplified schematic input voltage protection although not shown on the simplified schematic, esd protec- tion diodes are connected from each input to each power supply rail. these diodes are normally reverse biased, but will turn on if either input voltage exceeds either supply rail by more than +0.6 v. should this condition occur, the input current should be limited to less than 5 ma. this can be done by placing a resistor in series with the input(s). the minimum resistor value should be: r v ma in in max 3 , 5 (1) output phase reversal the ad8591/ad8592/ad8594 are immune to output voltage phase reversal with an input voltage within the supply voltages of the device. however, if either of the devices inputs exceeds +0.6 v outside of the supply rails, the output could exhibit phase reversal. this is due to the esd protection diodes be- coming forward biased, thus causing the polarity of the input terminals of the device to switch. the technique recommended in the input overvoltage protection section should be applied in applications where the possibility of input voltages exceeding the supply voltages exists. output short circuit protection to achieve high output current drive and rail-to-rail performance, the outputs of the ad859x family do not have internal short cir- cuit protection circuitry. although these amplifiers are designed to sink or source as much as 250 ma of output current, shorting the output directly to the positive supply could damage or destroy the device. to protect the output stage, the maximum output current should be limited to 250 ma. by placing a resistor in series with the output of the amplifier as shown in figure 30, the output current can be limited. the minimum value for r x can be found from equation 2. r v ma x sy 3 250 (2) for a +5 v single supply application, r x should be at least 20 w . because r x is inside the feedback loop, v out is not affected. the tradeoff in using r x is a slight reduction in output voltage swing under heavy output current loads. r x will also increase the effec- tive output impedance of the amplifier to r o + r x , where r o is the output impedance of the device. +5v r x 20 v v out v in ad8592 figure 30. output short circuit protection power dissipation although the ad859x family of amplifiers are able to provide load currents of up to 250 ma, proper attention should be given to not exceeding the maximum junction temperature for the device. the equation for finding the junction temperature is given as: tp t diss a a jj =+ q (3) where t j = ad859x junction temperature p diss = ad859x power dissipation q j a = ad859x junction-to-ambient thermal resistance of the package; and t a = the ambient temperature of the circuit
ad8591/ad8592/ad8594 C9C rev. a in any application, the absolute maximum junction temperature must be limited to +150 c. if this junction temperature is ex- ceeded, the device could suffer premature failure. if the output voltage and output current are in phase, for example, with a purely resistive load, the power dissipated by the ad859x can be found as: pi vv iss sy out d load = () (4) where i load = ad859x output load current v sy = ad859x supply voltage; and v out = the output voltage by calculating the power dissipation of the device and using the thermal resistance value for a given package type, the maximum allowable ambient temperature for an application can be found using equation 3. capacitive loading the ad859x exhibits excellent capacitive load driving capabilities and can drive up to 10 nf directly. although the device is stable with large capacitive loads, there is a decrease in amplifier band- width as the capacitive load increases. figure 31 shows a graph of the ad8592 unity gain bandwidth under various capacitive loads. capacitive load C nf 4 3.5 0 0.01 100 0.1 bandwidth C mhz 110 2 1.5 1 0.5 3 2.5 v s = 6 2.5v r l = 1k v t a = +25 8 c figure 31. unity gain bandwidth vs. capacitive load when driving heavy capacitive loads directly from the ad859x output, a snubber network can be used to improve transient response. this network consists of a series r-c connected from the amplifiers output to ground, placing it in parallel with the capacitive load. the configuration is shown in figure 32. al- though this network will not increase the bandwidth of the am- plifier, it will significantly reduce the amount of overshoot, as shown in figure 33. +5v r s 5 v v out v in 100mv p-p ad8592 c l 47nf c s 1 m f figure 32. configuration for snubber network to compensate for capacitive loads 10 0% 10 m s 50mv 100 90 50mv 47nf load only snubber in circuit figure 33. snubber network reduces overshoot and ringing caused from driving heavy capacitive loads the optimum values for the snubber network should be determined empirically based on the size of the capacitive load. table i shows a few sample snubber network values for a given load capacitance. table i. snubber networks for large capacitive loads load capacitance snubber network (c l )(r s , c s ) 0.47 nf 300 w , 0.1 m f 4.7 nf 30 w , 1 m f 47 nf 5 w , 1 m f a pc-98 compliant headphone/speaker amplifier because of its high output current performance and shutdown feature, the ad8592 makes an excellent amplifier for driving an audio output jack in a computer application. figure 34 shows how the ad8592 can be interfaced with an ac97 codec to drive headphones or speakers. u1-a r2 2k v 4 c1 100 m f +5v 1 10 2 3 5 +5v v dd v dd left out ad1881 (ac97) right out v ss r4 20 v +5v r1 100k v 7 8 6 9 r5 20 v c2 100 m f note: additional pins omitted for clarity u1-b u1 = ad8592 r3 2k v nc 28 35 36 figure 34. a pc-98 compliant headphone/line out amplifier when headphones are plugged into the jack, the normalizing con- tacts disconnect from the audio contacts. this allows the voltage to the ad8592 shutdown pins to be pulled up to +5 v, activating the amplifiers. with no plug in the output jack, the shutdown voltage is pulled to 100 mv through the r1 and r3 + r5 voltage divider. this powers the ad8592 down when it is not needed, saving current from the power supply or battery.
ad8591/ad8592/ad8594 C10C rev. a if gain is required from the output amplifier, four additional resistors should be added as shown in figure 35. the gain of the ad8592 can be set as: a r r v = 7 6 (5) u1-a r2 2k v 4 c1 100 m f +5v 1 10 2 3 5 +5v v dd v dd left out ad1881 (ac97) right out v ss r4 20 v +5v r1 100k v 7 8 6 9 r5 20 v c2 100 m f note: additional pins omitted for clarity u1-b u1 = ad8592 r3 2k v r7 20k v r7 20k v v ref r6 10k v r6 10k v a v = = +6db with values shown r7 r6 nc 38 35 27 36 figure 35. a pc-98 compliant headphone/line out amplifier with gain input coupling capacitors are not required for either circuit as the reference voltage is supplied from the ad1881. r4 and r5 help protect the ad8592 output in case the output jack or headphone wires accidentally get shorted to ground. the output coupling capacitors c1 and c2 block dc current from the headphones and create a high-pass filter with a corner frequency of: f cr r db l 3 1 214 = + () p (6) where r l is the resistance of the headphones. a combined microphone and speaker amplifier for cellphone and portable headsets the dual amplifiers in the ad8592 make an efficient design for interfacing with a headset containing a microphone and speaker. figure 36 demonstrates a simple method for constructing an interface to a codec. u1-a 4 +5v 1 10 2 3 5 c2 10 m f u1 = ad8592 7 8 6 9 r5 10k v u1-b r6 10k v ( optional ) r4 10k v from codec mono out (or left out) to codec r3 100k v v ref from codec mic + speaker jack r1 2.2k v +5v r2 10k v r8 100k v +5v c1 0.1 m f nc (right out) r7 1k v figure 36. a speaker/mic headset amplifier circuit u1-a is used as a microphone preamplifier, where the gain of the preamplifier is set as r3/r2. r1 is used to bias an electret microphone and c1 blocks any dc voltages from the amplifier. u1-b is the speaker amplifier, and its gain is set at r5/r4. to sum a stereo output, r6 should be added, equal in value to r4. using the same principle as described in the previous section, the normalizing contact on the microphone/speaker jack can be used to put the ad8592 into shutdown when the headset is not plugged in. the ad8592 shutdown inputs can also be con- trolled with ttl or cmos compatible logic, allowing micro- phone or speaker muting if desired. an inexpensive sample-and-hold circuit the independent shutdown control of each amplifier in the ad8592 allows a degree of flexibility in circuit design. one par- ticular application for which this feature is useful is in designing a sample-and-hold circuit for data acquisition. figure 37 shows a schematic of a simple, yet extremely effective sample-and-hold circuit using a single ad8592 and one capacitor. v in u1-a c1 1nf u1-b sample and hold output +5v 1 2 3 5 9 8 7 6 sample clock u1 = ad8592 +5v 4 10 figure 37. an efficient sample-and-hold circuit
ad8591/ad8592/ad8594 C11C rev. a the u1-a amplifier is configured as a unity gain buffer driving a 1 nf capacitor. the input signal is connected to the noninverting input, while the sample clock controls the shutdown for that amplifier. when the sample clock is high, the u1-a amplifier is active and the output follows v in . once the sample clock goes low, u1-a shuts down with the output of the amplifier going to a high impedance state, holding the voltage on the c1 capacitor. the u1-b amplifier is used as a unity gain buffer to prevent load- ing on c1. because of the low input bias current of the u1-b cmos input stage and the high impedance state of the u1-a output in shutdown, there is very little voltage droop from c1 during the hold period. this circuit can be used with sample frequencies as high as 500 khz and as low as below 1 hz. even lower voltage droop can be achieved for very low sample rates by increasing the value of c1. direct access arrangement for pcmcia modems (telephone line interface) figure 38 illustrates a +5 v transmit/receive telephone line interface for 600 w systems. it allows full duplex transmission of signals on a transformer-coupled 600 w line in a differential manner. amplifier a1 provides gain that can be adjusted to meet the modem output drive requirements. both a1 and a2 are configured to apply the largest possible signal on a single supply to the transformer. because of the ad8594s high output current drive and low dropout voltages, the largest signal avail- able on a single +5 v supply is approximately 4.5 v p-p into a 600 w transmission system. amplifier a3 is configured as a difference amplifier for two reasons: (1) it prevents the transmit signal from interfering with the receive signal and (2) it extracts the receive signal from the transmission line for amplification by a4. amplifier a4s gain can be adjusted in the same manner as a1s to meet the modems input signal requirements. standard resistor values permit the use of sip (single in-line package) format resistor arrays. couple this with the ad8594 16-lead tssop or soic footprint, and this circuit offers a compact, cost effective solution. r7 10k v r8 10k v +5v 6.2v 6.2v transmit txa receive rxa c1 0.1 m f r1 10k v r2 9.09k v 2k v p1 tx gain adjust a1 a2 a3 a4 a1, a2 = 1/2 ad8592 a3, a4 = 1/2 ad8592 r3 360 v 1:1 t1 to telephone line 1 2 3 9 8 7 2 3 1 8 7 9 10 m f r5 10k v r6 10k v r9 10k v r14 14.3k v r10 10k v r11 10k v r12 10k v r13 10k v c2 0.1 m f p2 rx gain adjust 2k v z o 600 v midcom 671-8005 shutdown 6 5 6 5 figure 38. a single supply direct access arrangement for pcmcia modems single supply differential line driver figure 39 shows a single supply differential line driver circuit that can drive a 600 w load with less than 0.7% distortion from 20 hz to 15 khz with an input signal of 4 v p-p and a single +5 v supply. the design uses an ad8594 to mimic the performance of a fully balanced transformer based solution. however, this design occu- pies much less board space while maintaining low distortion and can operate down to dc. like the transformer based design, either output can be shorted to ground for unbalanced line driver applica- tions without changing the circuit gain of 1. r l 600 v c1 22 m f a2 9 8 7 3 1 2 a1 +5v r1 10k v r2 10k v r11 10k v r7 10k v 8 7 7 a1 +5v +5v r8 100k v r9 100k v c2 1 m f r12 10k v r14 50 v a2 1 2 3 r3 10k v r6 10k v r13 10k v c3 47 m f v o1 v o2 c4 47 m f a1, a2 = 1/2 ad8592 gain = r3 r2 set: r7, r10, r11 = r2 set: r6, r12, r13 = r3 v in r10 10k v r5 50 v 10 4 10 4 9 figure 39. a low noise, single supply differential line driver r8 and r9 set up the common-mode output voltage equal to half of the supply voltage. c1 is used to couple the input signal and can be omitted if the inputs dc voltage is equal to half of the supply voltage. the circuit can also be configured to provide additional gain if desired. the gain of the circuit is: a v v r r v out in == 3 2 (7) where: v out = v o1 Cv o2 , r2 = r7 = r10 = r11 and, r3 = r6 = r12 = r13
ad8591/ad8592/ad8594 C12C rev. a spice model for the ad8591/ad8592/ad8594 amplifier the spice model for the ad8591/ad8592/ad8594 amplifier is one of the more realistic computer simulation macro-models available, providing a high degree of realism with respect to char- acteristics of the actual amplifier. this model, shown in listing 1, is based on typical values for the device and can be downloaded from analog devices internet site at www.analog.com . the model uses a common source output stage to provide rail- to-rail performance. this allows realistic simulation of open- loop gain dependency on load resistance as well as maximum output voltage versus output current. two differential pairs are used in the input stage of the model, simulating the rail-to-rail input stage of the ad8591/ad8592/ad8594 amplifier. the eos voltage source establishes the input offset voltage and is also used to simulate the common-mode rejection power supply rejection, and input voltage noise characteristics for the model. in addition, g2, r2 and cf are used to help set the open-loop gain and gain-bandwidth product of the model. a number of secondary characteristics are also accurately por- trayed in the spice model. flicker noise is accurately modeled with the 1/f corner frequency set through the kf and af terms in the input stage transistors. c1 and c2 are used in the input section to create secondary poles to achieve an accurate phase margin characteristic for the model. the ad8591/ad8592/ad8594 shutdown circuitry is included in the model. switches s1 through s7 deactivate the op amp circuitry in shutdown mode. the logic threshold for the shut- down circuitry is accurately modeled through the vswitch model parameters near the end of the listing. the active supply current versus supply voltage is also modeled through the volt- age-controlled current source gsy. characteristics of this model are based on typical values for the ad8591/ad8592/ad8594 amplifier at +27 c. the models characteristics are optimized specifically at +27 c, and may lose accuracy at different simulation temperatures.
ad8591/ad8592/ad8594 C13C rev. a listing 1: ad859x spice macro-model * ad8592 spice macro-model typical values * 9/98, ver. 1 * tam / adsc * * copyright 1998 by analog devices * * refer to readme.doc file for license * statement. use of this * model indicates your acceptance of the * terms and provisions in * the license statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | shutdown * | | | || | .subckt ad8592 1 2 99 50 45 80 * * input stage * m1 4 1 3 3 pix l=0.8e-6 w=125e-6 m2 6 7 3 3 pix l=0.8e-6 w=125e-6 rc1 4 50 4e3 rc2 6 50 4e3 c1 4 6 2e-12 i1 99 8 100e-6 m3 10 1 12 12 nix l=0.8e-6 w=125e-6 m4 11 7 12 12 nix l=0.8e-6 w=125e-6 rc3 10 99 4e3 rc4 11 99 4e3 c2 10 11 2e-12 i2 13 50 100e-6 eos 7 2 poly(3) (21,98) (73,98) (61,0) +1e-3 1 1 1 ios 1 2 2.5e-12 v1 99 9 0.9 d1 3 9 dx v2 14 50 0.9 d2 14 12 dx s1 3 8 (82,98) sopen s2 99 8 (98,82) sclose s3 12 13 (82,98) sopen s4 13 50 (98,82) sclose * * cmrr=64db, zero at 20khz * ecm1 20 98 poly(2) (1,98) (2,98) 0 .5 .5 rcm1 20 21 79.6e3 ccm1 20 21 100e-12 rcm2 21 98 50 * * psrr=80db, zero at 200hz * rps1 70 0 1e6 rps2 71 0 1e6 cps1 99 70 1e-5
ad8591/ad8592/ad8594 C14C rev. a cps2 50 71 1e-5 epsy 98 72 poly(2) (70,0) (0,71) 0 1 1 rps3 72 73 1.59e6 cps3 72 73 500e-12 rps4 73 98 80 * * internal voltage reference * eref 98 0 poly(2) (99,0) (50,0) 0 .5 .5 gsy 99 50 poly(1) (99,50) 20e-6 10e-7 * * shutdown section * e1 81 98 (80,50) 1 r1 81 82 1e3 c3 82 98 1e-9 * * voltage noise reference of 30nv/rt(hz) * vn1 60 0 0 rn1 60 0 16.45e-3 hn 61 0 vn1 30 rn2 61 0 1 * * gain stage * g2 98 30 poly(2) (4,6) (10,11) 0 2.19e-5 +2.19e-5 r2 30 98 13e6 cf 45 30 5e-12 s5 30 98 (98,82) sclose d3 30 31 dx d4 32 30 dx v3 99 31 0.6 v4 32 50 0.6 * * output stage * m5 45 46 99 99 pox l=0.8e-6 w=16e-3 m6 45 47 50 50 nox l=0.8e-6 w=16e-3 eg1 99 48 poly(1) (98,30) 1.06 1 eg2 49 50 poly(1) (30,98) 1.05 1 rg1 48 46 10e3 rg2 49 47 10e3 s6 46 99 (98,82) sclose s7 47 50 (98,82) sclose * * models * .model pix pmos (level=2,kp=20e-6,vto=-0.7, lambda=0.01,af=1,kf=1e-31) .model nix nmos (level=2,kp=20e-6,vto=0.7, lambda=0.01,af=1,kf=1e-31) .model pox pmos (level=2,kp=8e-6,vto=-1, lambda=0.067) .model nox nmos (level=2,kp=13.4e-6,vto=1, lambda=0.067) .model sopen vswitch(von=2.4,voff=0.8, ron=10,roff=1e9) .model sclose vswitch(von=-0.8,voff=-2.4, ron=10,roff=1e9) .model dx d(is=1e-14) .ends ad8592
ad8591/ad8592/ad8594 C15C rev. a 0.199 (5.05) 0.187 (4.75) 1 10 6 5 pin 1 0.0197 (0.50) bsc 0.124 (3.15) 0.112 (2.84) 0.124 (3.15) 0.112 (2.84) 0.122 (3.10) 0.110 (2.79) seating plane 0.006 (0.15) 0.002 (0.05) 0.016 (0.41) 0.006 (0.15) 0.038 (0.97) 0.030 (0.76) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.022 (0.56) 0.021 (0.53) 0.120 (3.05) 0.112 (2.84)

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